In magnetic storage systems for computers, digital data serves to modulate the current in a read/write head coil so that a sequence of corresponding magnetic flux transitions are written onto the surface of a magnetic medium in concentric, radially spaced tracks at a predetermined baud rate. When reading this recorded data, the read/write head again passes over the magnetic medium and transduces the magnetic transitions into pulses in an analog signal that alternates in polarity. These pulses are then decoded by read channel circuitry to reproduce the digital data.
Decoding the pulses into a digital sequence can be performed by a simple peak detector in a conventional analog read channel or, as in more recent designs, by a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interference (ISI) and are less susceptible to noise. As a result, discrete time sequence detectors increase the capacity and reliability of the storage system.
There are several well-known discrete time sequence detection methods including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, maximum likelihood sequence detection (MLSD), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF).
In conventional peak detection schemes, analog circuitry, responsive to threshold crossing or derivative information, detects peaks in the continuous time analog signal generated by the read head. The analog read signal is "segmented" into bit cell periods and interpreted during these segments of time. The presence of a peak during the bit cell period is detected as a "1" bit, whereas the absence of a peak is detected as a "0" bit. The most common errors in detection occur when the bit cells are not correctly aligned with the analog pulse data. Timing recovery, then, adjusts the bit cell periods so that the peaks occur in the center of the bit cells on average in order to minimize detection errors. Since timing information is derived only when peaks are detected, the input data stream is normally run length limited (RLL) to limit the number of consecutive "0" bits.
As the pulses are packed closer together on the concentric data tracks in the effort to increase data density, detection errors can also occur due to intersymbol interference, a distortion in the read signal caused by closely spaced overlapping pulses. This interference can cause a peak to shift out of its bit cell, or its magnitude to decrease, resulting in a detection error. The ISI effect is reduced by decreasing the data density or by employing an encoding scheme to ensure that a minimum number of "0" bits occur between "1" bits. For example, a (d,k) run length limited (RLL) code constrains to d the minimum number of "0" bits between "1" bits, and to k the maximum number of consecutive "0" bits. A typical RLL (1,7) 2/3 rate code encodes 8 bit data words into 12 bit codewords to satisfy the (1,7) constraint.
Sampled amplitude detection, such as partial response (PR) with Viterbi detection, allows for increased data density by compensating for intersymbol interference and increasing channel noise immunity. Unlike conventional peak detection systems, sampled amplitude recording detects digital data by interpreting, at discrete time instances, the actual value of the pulse data. A sampling device samples the analog read signal at the baud rate (code bit rate) and an equalizing filter equalizes the sample values according to a desired partial response. A discrete time sequence detector, such as a Viterbi detector, interprets the equalized sample values in context to determine a most likely sequence for the data, i.e., maximum likelihood sequence detection (MLSD). In this manner, the effect of ISI and channel noise can be taken into consideration during the detection process, thereby decreasing the probability of a detection error. This increases the effective signal-to-noise ratio and, for a given (d,k) constraint, allows for significantly higher data density as compared to conventional analog peak detection read channels.
Similar to conventional peak detection systems, sampled amplitude detection requires timing recovery in order to correctly extract the digital sequence. Rather than process the continuous signal to align peaks to the center of bit cell periods as in peak detection systems, sampled amplitude systems synchronize the pulse samples to the baud rate. In prior art sampled amplitude read channels, timing recovery synchronizes a sampling clock by minimizing an error between the signal sample values and estimated sample values. A pulse detector or slicer determines the estimated sample values from the read signal samples. Even in the presence of ISI the sample values can be estimated and, together with the signal sample values, used to synchronize the sampling of the analog pulses in a decision-directed feedback system.
A phase-locked loop (PLL) normally implements the decision-directed feedback system to control timing recovery in sampled amplitude read channels. A phase detector generates a phase error based on the difference between the estimated samples and the read signal samples. A loop filter filters the phase error, and the filtered phase error operates to synchronize the channel samples to the baud rate.
The timing recovery circuits generally include phase selectors to select the appropriate phase to be interpolated. FIG. 1 illustrates one prior art design of a phase selector circuit. This phase selector circuit 100 takes advantage of the staggered nature of two parallel decode paths in producing the CLK_PHSEL_OUT signals. In this way, at least one transmission gate is turned on at any time, and no high impedance is seen by the interpolator drivers. As illustrated, flip-flop 102 and inverter 104 form a divide-by-two block. The clock 2 signal output from the flip-flop 102 is one-half of the clock signal input into flip-flop 102. When the clock 2 signal is low, and the clock signal is high, the NEXT_PHASE signal is latched into flip-flop 106.
During the next rising clock transition, a feedback latch circuit 106 will keep the output of latch circuit 106, for a duration of one additional clock cycle. Thus, the next phase signal is output from the latch circuit 106. Meanwhile, the subsequent NEXT_PHASE signal is latched into flip-flop 108. The cycle repeats, alternating between flip-flops. The output of flip-flop 106 is input into decode circuit 110, which decodes a 6-bit word, NEXT_PHASE (5:0) into "one hot" 64-bit word, and the output of flip-flop 108 is input to decode circuit 112. The output of decode circuit 110 and decode circuit 112 is input to OR circuit 114. The OR circuit 114 combines the two decoded signals PH_OUTA (phase out of decode A) and PH_OUTB (phase out of decode B) to produce the output of CLK_PHSEL_OUT signal. FIG. 1 illustrates the output signals. It can be readily seen that using these gating signals, the clock output from the transmission gate multiplexer effectively is the interpolated clock signals of the two simultaneously selected phase clock signals. The effective clock phase jump is only half of what was intended and, therefore, the gain is reduced by half.
It is desirable to achieve a glitchless phase selector, one which has no point in time when no phase is being selected.